1. Field of the Invention
The present invention is directed generally to a buffer and, more particularly, to a buffer with a fast edge propagation.
2. Description of the Background
In a device, such as a semiconductor device, it is desirable to include a buffer which buffers the device input signals before they are communicated to the internal circuitry of the device. A buffer typically adapts the device input signals to internally required signal properties, such as signal voltage levels and transition delays, that must be present for internal circuitry to operate correctly. On devices which contain certain circuits, such as wide random access memory (RAM) circuits, input buffers must be placed around the die because the input/output pads are spread around the device.
When input buffers buffer certain time-dependent signals, such as the system clock signal input to a double data rate RAM, it is important to have a fast clock to data time (i.e. tKQ, tKHQV, and clock to out prop delay) on both edges of the clock. When conventional buffers, PLL circuits, or DLL circuits are used in such applications, there is no manner in which to stop the clock, there is excess capacitance on the lines, and there is a certain amount of clock distortion. Thus, there is a need for a buffer that can provide a fast clock to data time while allowing for clock stopping, providing low capacitance on the lines, and introducing a minimal amount of clock distortion.